Pre-silicon compatibility lab for AI appliance vendors to de-risk semi-custom GPU programs before tapeout.

1. OXMIQ's 35 million dollar Series A and 60 million dollars of total funding make licensable GPU IP a real procurement category, so evaluation projects can start before finished chips ship.
2. CUDA compatibility means buyers can start from workload proof instead of a full stack rewrite, making software-assurance tooling a practical first spend.
3. OxQuilt and OxPython explicitly target customers without full chip programs or code rewrites, which opens the market to system vendors that will need outside proof tooling.
4. Reducing data movement and energy costs is central to the OXMIQ pitch, so semi-custom silicon decisions are becoming gross-margin and power decisions now, not future science projects.
5. Jim Keller's board role and strategic backers including Samsung Catalyst Fund, MediaTek, and Pegatron reduce the credibility gap enough that first-time buyers can justify serious evaluations.

Catalyst. OXMIQ's funded pitch is that customers can license CUDA-compatible GPU IP and avoid a full chip program or code rewrite, which means semi-custom accelerator evaluations are moving forward now while buyers still lack a trusted proof layer.

The product plugs into a customer's production inference stack and captures representative CUDA kernels, model graphs, batch shapes, and memory traces. It replays those workloads against vendor simulators, compiler toolchains, and emulation targets from OXMIQ-like IP suppliers, then scores portability, memory pressure, and projected perf-per-watt before tapeout. For technical buyers, it highlights missing kernels, likely orchestration bottlenecks, and which workloads should stay on incumbent GPUs. For executives, it generates an assurance memo that ties software compatibility risk to BOM, energy, and program-timeline assumptions. The first deployment is a six-week evaluation around one planned accelerator card, giving the customer a credible funding decision before they hire a larger silicon team.

What's different. This is not another EDA suite, compiler, or chip-IP vendor. The company wins by owning the pre-silicon proof workflow around real customer workloads: capture, replay, risk scoring, and executive decision packs across multiple licensable-accelerator suppliers. Its moat compounds through a proprietary corpus of portability failures, kernel gaps, and perf-per-watt outcomes that neither individual IP vendors nor consultants can see across programs.

Jobs to be done

flowchart LR
  Buyer[AI appliance VP] --> Pain[Uncertain CUDA and margin risk on new silicon]
  Pain --> Product[Pre-silicon compatibility lab]
  Product --> Outcome[Confident go or no-go before tapeout]

Executive takeaways

• The wedge is real because licensable and semi-custom AI silicon is becoming easier to buy, but the near-term market is still a concentrated, high-value niche rather than a broad software category.
• Private AI and AI factory offers from Dell, HPE, Penguin, and Lenovo show the right beachhead accounts already exist outside hyperscalers.
• The customer pain is not just simulation cost; it is the lack of a neutral proof layer that connects real CUDA workloads to tapeout, BOM, power, and bring-up risk.
• Synopsys, Siemens, Cadence, and the IP vendors are strong adjacent incumbents, yet none is obviously positioned as the buyer-side system of record for accelerator go/no-go decisions.
• Year-3 revenue should be modeled conservatively because category velocity and simulator fidelity are the two biggest adoption constraints.

Market definition

Buyer-side pre-silicon workload-assurance software for semi-custom AI accelerator evaluations at OEMs and private-AI system builders. The initial market is narrow but attached to a fast-growing AI infrastructure base, not a generic EDA category [5][6][7][8][9][10][12][13][14].

Customer and buyer

The day-to-day user is the silicon, compiler, or platform-performance team that owns CUDA traces, model graphs, and bring-up risk. The economic buyer is usually the VP or GM of hardware or AI systems because the decision changes product margin, power, and tapeout exposure [1][9][10][11][13][14][44][45].

Buying triggers

• An AI appliance SKU or private-inference rack misses gross-margin or power targets under a mainstream GPU design, forcing evaluation of alternative accelerator economics. [5][6][9][10][12][13][14][43][44][45]
• A licensable or semi-custom accelerator path becomes credible because vendors promise CUDA-compatible software continuity and faster custom-compute development. [1][2][3][19][20][22][94][95]
• Leadership wants an auditable go or no-go before hiring a larger silicon team or locking a tapeout budget, which pushes teams toward emulation, profiling, and workload replay. [26][27][28][29][31][32][33][34][35]

Willingness to pay

Willingness to pay is credible because target accounts are already committing budget to AI factory infrastructure, private AI deployments, custom silicon programs, and hardware-assisted verification. A vendor-neutral assurance layer can attach to those existing line items by reducing the chance of funding the wrong accelerator program or discovering portability gaps after tapeout. [1][7][8][22][26][27][28][31][44]

Category dynamics

Growth signal 20%+ YoY AI server shipment growth through 2026

Validation signals

• OXMIQ’s $35M Series A and $60M total capital show investors believe licensable GPU IP is now a real category rather than a pure consulting story.
• TrendForce expects 2026 AI server shipments to grow more than 20% to 28%, with rising ASIC share and sovereign-cloud demand.
• Dell, HPE, Penguin, and Lenovo are already packaging private AI or AI factory offers, which creates a plausible beachhead outside hyperscalers.
• MLPerf remains the common external benchmark language, which makes a vendor-neutral trace-to-benchmark translation layer useful instead of redundant.

Regulatory & technical constraints

• Advanced-computing export controls can limit cross-border collaboration, artifact sharing, and supplier choice for sensitive accelerator evaluations.
• Chiplet packaging and interconnect standards such as UALink and CXL mean replay models must account for system topology, not just accelerator core claims.
• CUDA, driver, and ROCm version compatibility materially affect whether portability conclusions hold across customer environments.
• Rack power, liquid cooling, and whole-system integration can decide whether an accelerator program works economically even when the core architecture looks attractive.

Adjacent competition is strong, but fragmented. Synopsys, Siemens, and Cadence sell emulation, prototyping, and virtual-platform stacks; OXMIQ, Arm, and Marvell make semi-custom silicon more feasible; OEM AI factory vendors package infrastructure. The open space is a neutral layer that replays a buyer’s real workloads across these toolchains and turns the result into a procurement-quality go or no-go packet [1][2][19][20][22][26][27][28][29][31][32][33].

Why incumbents do not win by default

• Licensable GPU and custom-compute platforms. OXMIQ, Arm, and Marvell make semi-custom silicon more feasible, but their economic incentive is to validate their own path rather than compare multiple suppliers on a buyer's real workload mix.
• Hardware-assisted verification suites. Synopsys, Siemens, and Cadence already own emulation, prototyping, and virtual bring-up, yet they sell engineering tooling rather than a procurement-quality assurance layer for OEM accelerator choices.
• Private AI infrastructure OEMs. Dell, HPE, Penguin, and Lenovo package AI factory infrastructure and know the buyer relationship, but they do not by default own cross-vendor semi-custom accelerator evaluation against customer traces.
• In-house compiler and performance teams. Internal teams can profile and port workloads, but the fetched material shows why those workflows still depend on scarce tooling and careful version-specific compatibility work.
• Benchmark-only substitutes. MLPerf is valuable for baseline comparison, but standardized benchmark suites are not a substitute for replaying an OEM's actual model graph, batch profile, and memory behavior.

Licensable GPU IP makes semi-custom AI silicon plausible for non-hyperscaler OEMs, but it shifts the hardest decision from chip design to workload proof: whether a buyer's actual CUDA stack will port and hit BOM and power targets before tapeout. The first customer is a 300-800 person AI appliance vendor or regional server OEM selling private inference racks and missing gross-margin targets under an Nvidia-based design. The company sells a pre-silicon workload replay lab that captures production CUDA traces, model graphs, and memory profiles, replays them against partner simulators and compiler outputs, and delivers a go or no-go assurance pack for one accelerator program in roughly six weeks. Research supports the demand side — Dell, HPE, Penguin, and Lenovo already package private-AI and AI-factory systems — and the supply side — OXMIQ, Arm, and Marvell make semi-custom compute more feasible — but it also shows the near-term market is a concentrated, high-value niche rather than a broad software category. The researched market sizing suggests a TAM of about $180.0M, a SAM of about $45.0M, and a reachable year-3 SOM of about $3.6M, so the venture case depends on expanding from one evaluation workflow into post-silicon calibration and cross-vendor compatibility. The wedge is credible because no incumbent clearly owns the neutral buyer-side system of record connecting customer traces to tapeout, BOM, power, and bring-up risk; EDA vendors sell tooling and IP vendors sell their own path. The biggest unresolved questions are whether enough OEMs will actually fund first semi-custom accelerator evaluations in 2026-2028 and whether neutral third parties can get sufficient simulator and compiler access from the emerging IP ecosystems. This plan therefore treats the next 18 months as a proof phase focused on 2-3 paid design partners, 2-3 toolchain integrations, and evidence that pre-silicon predictions are trusted enough to convert into annual program subscriptions.

Problem

• AI appliance vendors and server OEMs increasingly see Nvidia BOM, rack power, and roadmap dependence compressing gross margin on inference systems, yet a semi-custom accelerator decision still requires a multimillion-dollar tapeout commitment.
• Today's alternative is fragmented across consultant studies, vendor benchmarks, spreadsheet ROI models, and ad-hoc simulator runs, so no one produces a neutral replay of the buyer's actual workloads before the funding decision.
• Missing CUDA, memory, or orchestration gaps often surface only during bring-up, when the customer has already spent the capital and hired the larger silicon team.

Solution

• Capture representative CUDA traces, model graphs, batch shapes, and memory profiles on customer-controlled infrastructure, then normalize them for replay against one candidate accelerator program.
• Run those workloads through licensable-GPU simulators, compiler toolchains, and emulation targets to score portability, memory pressure, and projected perf-per-watt before tapeout.
• Deliver an executive assurance pack that ties technical findings to BOM, power, and program-timeline assumptions, then extend into first-silicon telemetry to calibrate the model and support renewal.

Why we win

• The company is vendor-neutral in a market where IP suppliers are incentivized to prove their own architecture and EDA incumbents sell engineering tooling rather than a buyer-side go or no-go workflow.
• A growing corpus of anonymized workload traces, portability failures, and first-silicon calibration data compounds across programs in a way that no single OEM, consultant, or IP vendor can see alone.
• The beachhead is narrow enough to show value quickly: one accelerator program, one buying trigger, and one six-week proof cycle tied to a hard tapeout decision.
• The product translates compiler and simulation output into procurement-quality decisions for VP Hardware and GM buyers, not just engineering dashboards for a lab team.

Milestones

flowchart LR
  Wedge[AI appliance semi-custom evaluation] --> MVP[Pre-silicon replay lab]
  MVP --> Proof[Trusted go or no-go assurance pack]
  Proof --> Expansion[Post-silicon calibration and multi-program expansion]

Founding team

Experiment roadmap

Risk assessment

What must be true

• At least 15-20 North American and European OEM or appliance accounts will fund a first semi-custom accelerator evaluation between 2026 and 2028.
• A neutral third party can obtain enough simulator, compiler, and trace-access rights from at least two accelerator ecosystems to run credible pilots.
• The product can capture and replay 80% or more of prioritized production workloads within six weeks on customer-controlled infrastructure.
• Pre-silicon predictions stay within a 15-20% error band versus emulator or first-silicon results on early programs.
• Economic buyers convert successful pilots into $200k-$350k annual per-program contracts from existing hardware or evaluation budgets.

Open diligence questions

• Which named AI appliance vendors or regional OEMs already have a funded 2027 accelerator evaluation on the roadmap?
• What simulator and compiler interfaces will OXMIQ-like or Arm and Marvell partner ecosystems actually expose to a neutral assurance layer?
• How will the company keep traces on customer-controlled infrastructure and still accumulate a reusable moat?
• What accuracy threshold makes a VP Hardware buyer trust a no-go memo enough to cancel or delay tapeout?
• Why can’t Synopsys, Siemens, Cadence, or the IP vendor bundle enough replay functionality to erase this wedge?
• Which budget owner signs first in practice: hardware GM, silicon lead, or platform-performance leader?

Model sanity

• Revenue engine. Base revenue comes from moving from 3 paid programs at Y1 exit to 11 by Q4Y3 while mature program value approaches the researched ~$300K annual SOM level.
• Must go right. The first two pilots must convert to annual subscriptions and at least two toolchain integrations must become reusable enough that one solutions-heavy team can support 7 active programs by Q4Y2 without crushing margin.
• Model breaks if. If sales cycles drift toward 150 days or gross margin stalls below about 68%, the downside case pushes the cash floor toward roughly $0.25M before the company has enough proof for the next round.
• Next-round proof. The next financing story is about 5 active paid programs by Q2Y2 plus 2 annual conversions, 2 working integrations, and early calibration evidence that replay accuracy stays inside the 15%-20% error band.

Scenarios

Sensitivity

flowchart LR
  TargetAccounts[Target OEMs and AI appliance vendors] --> PaidPilots[Paid pilots]
  PaidPilots --> AnnualPrograms[Annual program subscriptions]
  AnnualPrograms --> Telemetry[Telemetry and cross-vendor modules]
  Telemetry --> Revenue[Revenue]
  Revenue --> GrossProfit[Gross profit]
  GrossProfit --> Cash[Cash and runway]

Flags: The base case reaches 11 active paid programs against a researched 12-program year-3 SOM, so there is little room for missed conversions inside the initial beachhead. · customersEop counts active paid accelerator programs rather than unique logos, so logo diversification is weaker than the headline count suggests through most of the model. · Gross margin only reaches the 70% target once simulator access, onboarding, and calibration workflows standardize; prolonged bespoke work would keep EBITDA negative. · No dedicated AE is added before Y4, so founder and partnerships bandwidth is a real gating factor in the sales-cycle downside case. · Cash is modeled as EBITDA; partner minimum-commit fees, deferred revenue timing, or lab-equipment capex could shift the actual trough earlier.

• Category forms slowly. If only a handful of system vendors pursue semi-custom GPU programs in the next two years, revenue could lag before the market matures. Mitigation: Start with design partners already evaluating one accelerator card and support adjacent emulator-based procurement decisions for broader hardware teams.
• IP-vendor bundling. OXMIQ or another licensable IP vendor could bundle basic compatibility replay into its own sales motion and narrow the standalone wedge. Mitigation: Stay vendor-neutral, benchmark across multiple suppliers, and own the buyer-side decision workflow and post-silicon telemetry that no single IP vendor can credibly provide.
• Simulation fidelity gap. Pre-silicon replay may miss real bring-up issues, which would damage trust if buyers treat the output as a guarantee. Mitigation: Position the product as auditable decision support, publish confidence bands, and pair pre-tapeout findings with first-silicon telemetry to continuously calibrate the models.